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Theoretical Computer Science
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Model checking
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Theoretical Computer Science
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TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Bounded Reachability Checking with Process Semantics
CONCUR '01 Proceedings of the 12th International Conference on Concurrency Theory
Lectures on Petri Nets I: Basic Models, Advances in Petri Nets, the volumes are based on the Advanced Course on Petri Nets
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
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CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Symbolic Model Checking of Infinite State Systems Using Presburger Arithmetic
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Encoding Planning Problems in Nonmonotonic Logic Programs
ECP '97 Proceedings of the 4th European Conference on Planning: Recent Advances in AI Planning
Bounded LTL model checking with stable models
Theory and Practice of Logic Programming
BMC via Dynamic Atomicity Analysis
ACSD '04 Proceedings of the Fourth International Conference on Application of Concurrency to System Design
CheckFence: checking consistency of concurrent data types on relaxed memory models
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Principles of Model Checking (Representation and Mind Series)
Principles of Model Checking (Representation and Mind Series)
Unfoldings: A Partial-Order Approach to Model Checking (Monographs in Theoretical Computer Science. An EATCS Series)
FCT '07 Proceedings of the 16th international symposium on Fundamentals of Computation Theory
Symbolic Step Encodings for Object Based Communicating State Machines
FMOODS '08 Proceedings of the 10th IFIP WG 6.1 international conference on Formal Methods for Open Object-Based Distributed Systems
Towards SMT Model Checking of Array-Based Systems
IJCAR '08 Proceedings of the 4th international joint conference on Automated Reasoning
Encoding Queues in Satisfiability Modulo Theories Based Bounded Model Checking
LPAR '08 Proceedings of the 15th International Conference on Logic for Programming, Artificial Intelligence, and Reasoning
Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
Monotonic Partial Order Reduction: An Optimal Symbolic Partial Order Reduction Technique
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Planning as satisfiability: parallel plans and algorithms for plan search
Artificial Intelligence
DiVinE 2.0: High-Performance Model Checking
HIBI '09 Proceedings of the 2009 International Workshop on High Performance Computational Systems Biology
Parameterized verification of infinite-state processes with global conditions
CAV'07 Proceedings of the 19th international conference on Computer aided verification
BEEM: benchmarks for explicit model checkers
Proceedings of the 14th international SPIN conference on Model checking software
Planning as satisfiability with relaxed ∃-step plans
AI'07 Proceedings of the 20th Australian joint conference on Advances in artificial intelligence
Peephole partial order reduction
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Pushing the envelope: planning, propositional logic, and stochastic search
AAAI'96 Proceedings of the thirteenth national conference on Artificial intelligence - Volume 2
Checking bounded reachability in asynchronous systems by symbolic event tracing
VMCAI'10 Proceedings of the 11th international conference on Verification, Model Checking, and Abstract Interpretation
SAT based bounded model checking with partial order semantics for timed automata
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Proving and explaining the unfeasibility of message sequence charts for hybrid systems
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
SMT-based scenario verification for hybrid systems
Formal Methods in System Design
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This paper discusses bounded model checking (BMC) for asynchronous systems. Bounded model checking is a technique that employs the power of efficient SAT and SMT solvers for model checking. The main contribution of this paper is the presentation of a simple modeling formalism independent way of translating an asynchronous system into a transition formula for three partial order semantics: the @?-step semantics, its generalization, the relaxed @?-step semantics, and a novel variant that combines the latter with the idea of process semantics. Step and process semantics have been introduced in earlier works for different low level asynchronous system formalisms to improve the efficiency of BMC. However, this paper is the first one showing how to translate the semantics for any asynchronous system modeling formalism including high-level data manipulation operations while encoding the independence of actions in a dynamic fashion. Thus, the approaches have been extended to cover a larger class of modeling formalisms. The technical approach uses the notion of a coherent encoding of the transition relation, making for a simple and elegant translation of the partial order semantics in question. The presented translations have been implemented and we present extensive empirical results comparing the efficiency of the different translations to each other as well as to an explicit state model checker DiVinE on its own BEEM benchmark suite.