A fast mutual exclusion algorithm
ACM Transactions on Computer Systems (TOCS)
Handbook of theoretical computer science (vol. B)
Symbolic model checking for real-time systems
Information and Computation
Act, and the rest will follow: exploiting determinism in planning as satisfiability
AAAI '98/IAAI '98 Proceedings of the fifteenth national/tenth conference on Artificial intelligence/Innovative applications of artificial intelligence
A machine program for theorem-proving
Communications of the ACM
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Efficient Data Structure for Fully Symbolic Verification of Real-Time Software Systems
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Timing Assumptions and Verification of Finite-State Concurrent Systems
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Verification of Timed Automata via Satisfiability Checking
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
Towards Bounded Model Checking for the Universal Fragment of TCTL
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
Kronos: A Model-Checking Tool for Real-Time Systems
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Tuning SAT Checkers for Bounded Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Benefits of Bounded Model Checking at an Industrial Setting
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Model-Checking for Real-Time Systems
FCT '95 Proceedings of the 10th International Symposium on Fundamentals of Computation Theory
A SAT Based Approach for Solving Formulas over Boolean and Linear Mathematical Propositions
CADE-18 Proceedings of the 18th International Conference on Automated Deduction
Two examples of verification of multirate timed automata with Kronos
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Heuristics based on unit propagation for satisfiability problems
IJCAI'97 Proceedings of the 15th international joint conference on Artifical intelligence - Volume 1
Integrating Boolean and Mathematical Solving: Foundations, Basic Algorithms, and Requirements
AISC '02/Calculemus '02 Proceedings of the Joint International Conferences on Artificial Intelligence, Automated Reasoning, and Symbolic Computation
Checking reachability properties for timed automata via SAT
Fundamenta Informaticae - Concurrency specification and programming
Bounded model checking for knowledge and real time
Proceedings of the fourth international joint conference on Autonomous agents and multiagent systems
MathSAT: Tight Integration of SAT and Mathematical Decision Procedures
Journal of Automated Reasoning
ACTLS properties and Bounded Model Checking
Fundamenta Informaticae
Bounded Model Checking with Parametric Data Structures
Electronic Notes in Theoretical Computer Science (ENTCS)
SAT-based Abstraction Refinement for Real-time Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
Bounded model checking for knowledge and real time
Artificial Intelligence
SAT-Based Reachability Checking for Timed Automata with Discrete Data
Fundamenta Informaticae - Special Issue on Concurrency Specification and Programming (CS&P)
Improved bounded model checking for the universal fragment of CTL
Journal of Computer Science and Technology
The COMPASS Approach: Correctness, Modelling and Performability of Aerospace Systems
SAFECOMP '09 Proceedings of the 28th International Conference on Computer Safety, Reliability, and Security
SAT-based Verification for Timed Component Connectors
Electronic Notes in Theoretical Computer Science (ENTCS)
Verifying Industrial Hybrid Systems with MathSAT
Electronic Notes in Theoretical Computer Science (ENTCS)
Efficient interpolant generation in satisfiability modulo theories
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Bounded Parametric Verification for Distributed Time Petri Nets with Discrete-Time Semantics
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
SAT-based (parametric) reachability for a class of distributed time Petri nets
Transactions on Petri nets and other models of concurrency IV
Exploiting symmetry in SMT problems
CADE'11 Proceedings of the 23rd international conference on Automated deduction
Exact incremental analysis of timed automata with an SMT-solver
FORMATS'11 Proceedings of the 9th international conference on Formal modeling and analysis of timed systems
Optimizing bounded model checking for linear hybrid systems
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
Bounded validity checking of interval duration logic
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
An incremental and layered procedure for the satisfiability of linear arithmetic logic
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Building efficient decision procedures on top of SAT solvers
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
SAT based bounded model checking with partial order semantics for timed automata
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
SAT-based verification for timed component connectors
Science of Computer Programming
Formal correctness, safety, dependability, and performance analysis of a satellite
Proceedings of the 34th International Conference on Software Engineering
Beyond lassos: complete SMT-Based bounded model checking for timed automata
FMOODS'12/FORTE'12 Proceedings of the 14th joint IFIP WG 6.1 international conference and Proceedings of the 32nd IFIP WG 6.1 international conference on Formal Techniques for Distributed Systems
SAT-Based Reachability Checking for Timed Automata with Discrete Data
Fundamenta Informaticae - Special Issue on Concurrency Specification and Programming (CS&P)
Improvements in SAT-based Reachability Analysis for Timed Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2003)
Checking Reachability Properties for Timed Automata via SAT
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P'2002), Part 2
ACTLS properties and Bounded Model Checking
Fundamenta Informaticae
Planning as satisfiability: Heuristics
Artificial Intelligence
SMT-Based induction methods for timed systems
FORMATS'12 Proceedings of the 10th international conference on Formal Modeling and Analysis of Timed Systems
Lemma localization: a practical method for downsizing SMT-interpolants
Proceedings of the Conference on Design, Automation and Test in Europe
Incremental language inclusion checking for networks of timed automata
FORMATS'13 Proceedings of the 11th international conference on Formal Modeling and Analysis of Timed Systems
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Enormous progress has been achieved in the last decade in the verification of timed systems, making it possible to analyze significant real-world protocols. An open challenge is the identification of fully symbolic verification techniques, able to deal effectively with the finite state component as well as with the timing aspects. In this paper we propose a new, symbolic verification technique that extends the Bounded Model Checking (BMC) approach for the verification of timed systems. The approach is based on the following ingredients. First, a BMC problem for timed systems is reduced to the satisfiability of a math-formula, i.e., a boolean combination of propositional variables and linear mathematical relations over real variables (used to represent clocks). Then, an appropriate solver, called MATHSAT, is used to check the satisfiability of the math-formula. The solver is based on the integration of SAT techniques with some specialized decision procedures for linear mathematical constraints, and requires polynomial memory. Our methods allow for handling expressive properties in a fully-symbolic way. A preliminary experimental evaluation confirms the potential of the approach.