Theoretical Computer Science
The algorithmic analysis of hybrid systems
Theoretical Computer Science - Special issue on hybrid systems
Automatic Symbolic Verification of Embedded Systems
IEEE Transactions on Software Engineering
Bounded Model Checking for Timed Systems
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Verification of Timed Automata via Satisfiability Checking
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Benefits of Bounded Model Checking at an Industrial Setting
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
A SAT Based Approach for Solving Formulas over Boolean and Linear Mathematical Propositions
CADE-18 Proceedings of the 18th International Conference on Automated Deduction
Lazy Theorem Proving for Bounded Model Checking over Infinite Domains
CADE-18 Proceedings of the 18th International Conference on Automated Deduction
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
Checking reachability properties for timed automata via SAT
Fundamenta Informaticae - Concurrency specification and programming
Accelerating Bounded Model Checking of Safety Properties
Formal Methods in System Design
Parallel SAT solving in bounded model checking
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Efficient scenario verification for hybrid automata
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Proving and explaining the unfeasibility of message sequence charts for hybrid systems
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
SMT-based scenario verification for hybrid systems
Formal Methods in System Design
Time-aware relational abstractions for hybrid systems
Proceedings of the Eleventh ACM International Conference on Embedded Software
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Bounded model checking (BMC) is an automatic verification method that is based on finitely unfolding the system's transition relation. BMC has been successfully applied, in particular, for discovering bugs in digital system design. Its success is based on the effectiveness of satisfiability solvers that are used to check for a finite unfolding whether a violating state is reachable. In this paper we improve the BMC approach for linear hybrid systems. Our improvements are tailored to lazy satisfiability solving and follow two complementary directions. First, we optimize the formula representation of the finite unfoldings of the transition relations of linear hybrid systems, and second, we accelerate the satisfiability checks by accumulating and generalizing data that is generated during earlier satisfiability checks. Experimental results show that the presented techniques accelerate the satisfiability checks significantly.