Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The shifting bottleneck procedure for job shop scheduling
Management Science
Theoretical Computer Science
Symbolic model checking for real-time systems
Information and Computation
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Checking that finite state concurrent programs satisfy their linear specification
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Symbolic Model Checking
Introduction to Algorithms
Logic-Based Methods for Optimization
PPCP '94 Proceedings of the Second International Workshop on Principles and Practice of Constraint Programming
On the Representation of Timed Polyhedra
ICALP '00 Proceedings of the 27th International Colloquium on Automata, Languages and Programming
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Efficient Guiding Towards Cost-Optimality in UPPAAL
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Partial Order Reductions for Timed Systems
CONCUR '98 Proceedings of the 9th International Conference on Concurrency Theory
Timing analysis of asynchronous circuits using timed automata
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Timing Assumptions and Verification of Finite-State Concurrent Systems
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
Kronos: A Model-Checking Tool for Real-Time Systems
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
IF: A Validation Environment for Timed Asynchronous Systems
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Job-Shop Scheduling Using Timed Automata
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Deciding Separation Formulas with SAT
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
CSL '99 Proceedings of the 13th International Workshop and 8th Annual Conference of the EACSL on Computer Science Logic
SAT-Based Procedures for Temporal Reasoning
ECP '99 Proceedings of the 5th European Conference on Planning: Recent Advances in AI Planning
A SAT Based Approach for Solving Formulas over Boolean and Linear Mathematical Propositions
CADE-18 Proceedings of the 18th International Conference on Automated Deduction
Lazy Theorem Proving for Bounded Model Checking over Infinite Domains
CADE-18 Proceedings of the 18th International Conference on Automated Deduction
Data-Structures for the Verification of Timed Automata
HART '97 Proceedings of the International Workshop on Hybrid and Real-Time Systems
Nordic Journal of Computing
The propositional formula checker HeerHugo
The propositional formula checker HeerHugo
Bounded Model Checking for Timed Systems
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
Checking reachability properties for timed automata via SAT
Fundamenta Informaticae - Concurrency specification and programming
Improvements in SAT-based Reachability Analysis for Timed Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2003)
ACTLS properties and Bounded Model Checking
Fundamenta Informaticae
Bounded Model Checking with Parametric Data Structures
Electronic Notes in Theoretical Computer Science (ENTCS)
Universality Analysis for One-Clock Timed Automata
Fundamenta Informaticae - Fundamentals of Software Engineering 2007: Selected Contributions
Exact incremental analysis of timed automata with an SMT-solver
FORMATS'11 Proceedings of the 9th international conference on Formal modeling and analysis of timed systems
Interoperability of constrained finite state automata
ACM SIGSOFT Software Engineering Notes
Optimizing bounded model checking for linear hybrid systems
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
Fast and flexible difference constraint propagation for DPLL(T)
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
SAT based bounded model checking with partial order semantics for timed automata
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
SDSAT: tight integration of small domain encoding and lazy approaches in a separation logic solver
TACAS'06 Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Universality Analysis for One-Clock Timed Automata
Fundamenta Informaticae - Fundamentals of Software Engineering 2007: Selected Contributions
Improvements in SAT-based Reachability Analysis for Timed Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2003)
Checking Reachability Properties for Timed Automata via SAT
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P'2002), Part 2
ACTLS properties and Bounded Model Checking
Fundamenta Informaticae
Incremental language inclusion checking for networks of timed automata
FORMATS'13 Proceedings of the 11th international conference on Formal Modeling and Analysis of Timed Systems
| Hi-index | 0.00 |
In this paper we show how to translate bounded-length verification problems for timed automata into formulae in difference logic, a propositional logic enriched with timing constraints. We describe the principles of a satisfiability checker specialized for this logic that we have implemented and report some preliminary experimental results.