Data-Structures for the Verification of Timed Automata

Region Encoding Diagram for Fully Symbolic Verification of Real-Time Systems

COMPSAC '00 24th International Computer Software and Applications Conference

Using MTBDDs for Compostion and Model Checking of Real-Time Systems

FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design

On the Representation of Timed Polyhedra

ICALP '00 Proceedings of the 27th International Colloquium on Automata, Languages and Programming

Efficient Data Structure for Fully Symbolic Verification of Real-Time Software Systems

TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000

Efficient Verification of Timed Automata with BDD-Like Data-Structures

VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation

The Impressive Power of Stopwatches

CONCUR '00 Proceedings of the 11th International Conference on Concurrency Theory

Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics

CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods

Verification of Timed Automata via Satisfiability Checking

FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2

Towards Bounded Model Checking for the Universal Fragment of TCTL

FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2

Timed Verification of Asynchronous Circuits

Concurrency and Hardware Design, Advances in Petri Nets

Improvements in BDD-Based Reachability Analysis of Timed Automata

FME '01 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods for Increasing Software Productivity

Efficient Timed Reachability Analysis Using Clock Difference Diagrams

CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification

Difference Decision Diagrams

CSL '99 Proceedings of the 13th International Workshop and 8th Annual Conference of the EACSL on Computer Science Logic

Automatic effective verification method for distributed and concurrent systems using timed language inclusion

Engineering of distributed control systems

Clock difference diagrams

Nordic Journal of Computing

Symbolic Verification and Analysis of Discrete Timed Systems

Formal Methods in System Design

Compact Data Structures and State-Space Reduction for Model-Checking Real-Time Systems

Real-Time Systems

Checking reachability properties for timed automata via SAT

Fundamenta Informaticae - Concurrency specification and programming

Symbolic Parametric Safety Analysis of Linear Hybrid Systems with BDD-Like Data-Structures

IEEE Transactions on Software Engineering

The octahedron abstract domain

Science of Computer Programming

Improvements in SAT-based Reachability Analysis for Timed Automata

Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2003)

SAT-based Reachability Checking for Timed Automata with Diagonal Constraints

Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2004)

Symbolic simulation of industrial real-time and embedded systems -experiments with the bluetooth baseband communication protocol

Journal of Embedded Computing - Real-Time and Embedded Computing Systems

Chain programming over difference constraints

Nordic Journal of Computing

Bounded Model Checking Real-Time Multi-agent Systems with Clock Differences: Theory and Implementation

Model Checking and Artificial Intelligence

Improvements for the Symbolic Verification of Timed Automata

FORTE '07 Proceedings of the 27th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems

Optimal Length Resolution Refutations of Difference Constraint Systems

Journal of Automated Reasoning

Predicate Diagrams for the Verification of Real-Time Systems

Electronic Notes in Theoretical Computer Science (ENTCS)

Sampled universality of timed automata

FOSSACS'07 Proceedings of the 10th international conference on Foundations of software science and computational structures

SDL as UML: why and what panel

UML'99 Proceedings of the 2nd international conference on The unified modeling language: beyond the standard

Verification, performance analysis and controller synthesis for real-time systems

FSEN'09 Proceedings of the Third IPM international conference on Fundamentals of Software Engineering

Symbolic model checking of finite precision timed automata

ICTAC'05 Proceedings of the Second international conference on Theoretical Aspects of Computing

SAT-based Reachability Checking for Timed Automata with Diagonal Constraints

Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2004)

Improvements in SAT-based Reachability Analysis for Timed Automata

Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2003)

Checking Reachability Properties for Timed Automata via SAT

Fundamenta Informaticae - Concurrency Specification and Programming (CS&P'2002), Part 2