Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
UPPAAL—a tool suite for automatic verification of real-time systems
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
Efficient and User-Friendly Verification
IEEE Transactions on Computers
Region Encoding Diagram for Fully Symbolic Verification of Real-Time Systems
COMPSAC '00 24th International Computer Software and Applications Conference
Symbolic Verification of Complex Real-Time Systems with Clock-Restriction Diagram
FORTE '01 Proceedings of the IFIP TC6/WG6.1 - 21st International Conference on Formal Techniques for Networked and Distributed Systems
Efficient Data Structure for Fully Symbolic Verification of Real-Time Software Systems
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Timing Assumptions and Verification of Finite-State Concurrent Systems
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Symbolic Model Checking for Distributed Real-Time Systems
FME '93 Proceedings of the First International Symposium of Formal Methods Europe on Industrial-Strength Formal Methods
Kronos: A Model-Checking Tool for Real-Time Systems
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Efficient Timed Reachability Analysis Using Clock Difference Diagrams
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
CSL '99 Proceedings of the 13th International Workshop and 8th Annual Conference of the EACSL on Computer Science Logic
Data-Structures for the Verification of Timed Automata
HART '97 Proceedings of the International Workshop on Hybrid and Real-Time Systems
Approximate reachability analysis of timed automata
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Efficient verification of real-time systems: compact data structure and state-space reduction
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
Symbolic Parametric Safety Analysis of Linear Hybrid Systems with BDD-Like Data-Structures
IEEE Transactions on Software Engineering
TCTL Inevitability Analysis of Dense-Time Systems: From Theory to Engineering
IEEE Transactions on Software Engineering
Improvements for the Symbolic Verification of Timed Automata
FORTE '07 Proceedings of the 27th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
Test Plan Generation for Concurrent Real-Time Systems Based on Zone Coverage Analysis
TestCom '08 / FATES '08 Proceedings of the 20th IFIP TC 6/WG 6.1 international conference on Testing of Software and Communicating Systems: 8th International Workshop
Time-Progress Evaluation for Dense-Time Automata with Concave Path Conditions
ATVA '08 Proceedings of the 6th International Symposium on Automated Technology for Verification and Analysis
TCTL inevitability analysis of dense-time systems
CIAA'03 Proceedings of the 8th international conference on Implementation and application of automata
Hypervolume approximation in timed automata model checking
FORMATS'07 Proceedings of the 5th international conference on Formal modeling and analysis of timed systems
Symbolic simulation-checking of dense-time automata
FORMATS'07 Proceedings of the 5th international conference on Formal modeling and analysis of timed systems
Symbolic verification of distributed real-time systems with complex synchronizations
ICFEM'05 Proceedings of the 7th international conference on Formal Methods and Software Engineering
An MTBDD-based implementation of forward reachability for probabilistic timed automata
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Symbolic model checking of finite precision timed automata
ICTAC'05 Proceedings of the Second international conference on Theoretical Aspects of Computing
Fast generic model-checking for data-based systems
FORTE'05 Proceedings of the 25th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
ACM Computing Surveys (CSUR)
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We investigate the efficiency of BDD-like data-structures for timed automata verification. We find that the efficiency is highly sensitive to the variable designs and canonical form definitions. We explore the two issues in details and propose to use CRD (Clock-Restriction Diagram) for timed automata state-space representation. We compare two canonical forms for zones, develop a procedure for quick zone-containment detection, and discuss the effect of variable-ordering of CRD. We implement our idea in our tool red 4.1 and carry out experiments to compare with other tools and red's previous version in both forward and backward analysis.