Efficient and User-Friendly Verification
IEEE Transactions on Computers
Region Encoding Diagram for Fully Symbolic Verification of Real-Time Systems
COMPSAC '00 24th International Computer Software and Applications Conference
Efficient Data Structure for Fully Symbolic Verification of Real-Time Software Systems
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Efficient Verification of Timed Automata with BDD-Like Data-Structures
VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation
Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Accurate Widenings and Boundedness Properties of Timed Systems
PSI '02 Revised Papers from the 4th International Andrei Ershov Memorial Conference on Perspectives of System Informatics: Akademgorodok, Novosibirsk, Russia
Beyond Region Graphs: Symbolic Forward Analysis of Timed Automata
Proceedings of the 19th Conference on Foundations of Software Technology and Theoretical Computer Science
Timed Verification of Asynchronous Circuits
Concurrency and Hardware Design, Advances in Petri Nets
Efficient Timed Reachability Analysis Using Clock Difference Diagrams
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
CSL '99 Proceedings of the 13th International Workshop and 8th Annual Conference of the EACSL on Computer Science Logic
Automatic Verification of Pointer Data-Structure Systems for All Numbers of Processes
FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume I - Volume I
Engineering of distributed control systems
Nordic Journal of Computing
Symbolic Parametric Safety Analysis of Linear Hybrid Systems with BDD-Like Data-Structures
IEEE Transactions on Software Engineering
TCTL Inevitability Analysis of Dense-Time Systems: From Theory to Engineering
IEEE Transactions on Software Engineering
TCTL inevitability analysis of dense-time systems
CIAA'03 Proceedings of the 8th international conference on Implementation and application of automata
Hypervolume approximation in timed automata model checking
FORMATS'07 Proceedings of the 5th international conference on Formal modeling and analysis of timed systems
Fast generic model-checking for data-based systems
FORTE'05 Proceedings of the 25th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
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A promising approach to formal verification of real-time systems is to use timed automata to model systems, and then to check whether certain "unsafe" states are reachable. Although theoretically appealing, this approach has significant practical problems because it requires expensive computation of reachable states. Fortunately computing a superset of reachable states is sometimes much cheaper. Replacing the set of reachable states with its superset is a conservative approximation, in the sense that it can occasionally cause a correct system to be declared incorrect, but can never cause an incorrect system to be declared correct. We propose two algorithms for computing a superset of reachable states of a timed automaton. Both algorithms involve only manipulation of Boolean functions, which are used to represent both sets of discrete state components and timing information. The algorithms offer different trade-offs between accuracy of approximation and efficiency of computation. Initial experimental results show that they are competitive with the best published results, but that further improvements are necessary to scale up to realistic systems.