Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Fairness
Modalities for model checking: branching time logic strikes back
Science of Computer Programming
Communication and concurrency
Introduction to algorithms
Timing assumptions and verification of finite-state concurrent systems
Proceedings of the international workshop on Automatic verification methods for finite state systems
Modeling and Verification of Time Dependent Systems Using Time Petri Nets
IEEE Transactions on Software Engineering
Theoretical Computer Science
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
A note on reliable full-duplex transmission over half-duplex links
Communications of the ACM
Symbolic Model Checking
Introduction To Automata Theory, Languages, And Computation
Introduction To Automata Theory, Languages, And Computation
TACS '97 Proceedings of the Third International Symposium on Theoretical Aspects of Computer Software
Timing Verification by Successive Approximation
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
A Verification Strategy for Timing-Constrained Systems
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Decidability of Bisimulation Equivalences for Parallel Timer Processes
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Verification of Real-Time Systems by Successive Over and Under Approximation
Proceedings of the 7th International Conference on Computer Aided Verification
Some Progress in the Symbolic Verification of Timed Automata
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
An Overview and Synthesis on Timed Process Algebras
Proceedings of the Real-Time: Theory in Practice, REX Workshop
Data-Structures for the Verification of Timed Automata
HART '97 Proceedings of the International Workshop on Hybrid and Real-Time Systems
Compositional and symbolic model-checking of real-time systems
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Approximate reachability analysis of timed automata
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
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In distributed and concurrent systems, the notions of fairness and time are important as follows: (1)Fairness is a mathematical abstraction in distributed and concurrent systems. Fairness abstracts the details of fair schedulers and the speeds of independent processors. (2)The distributed and concurrent systems have to meet certain hard real-time constraints, and the correctness of them depends on the actual values of the delays.In this paper, we propose the specification and verification method of fairness and time in distributed and concurrent systems as follows: (1)In order to specify fairness, an enable condition and a performed condition are attached to a finite set of states in our proposed specification method. (2)In order to effectively verify distributed and concurrent systems, we restrict timing constraints of timed automaton such that in cycles we must specify timing constraints about the clock variables after they are reset to zero.