Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
Utilizing symmetry when model-checking under fairness assumptions: an automata-theoretic approach
ACM Transactions on Programming Languages and Systems (TOPLAS)
Automatic Verification on the Large
HASE '98 The 3rd IEEE International Symposium on High-Assurance Systems Engineering
FORTE XII / PSTV XIX '99 Proceedings of the IFIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XII) and Protocol Specification, Testing and Verification (PSTV XIX)
Efficient Data Structure for Fully Symbolic Verification of Real-Time Software Systems
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Timing Assumptions and Verification of Finite-State Concurrent Systems
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Kronos: A Model-Checking Tool for Real-Time Systems
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Efficient Timed Reachability Analysis Using Clock Difference Diagrams
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Data-Structures for the Verification of Timed Automata
HART '97 Proceedings of the International Workshop on Hybrid and Real-Time Systems
Approximate reachability analysis of timed automata
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Efficient Verification of Timed Automata with BDD-Like Data-Structures
VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation
Symbolic Parametric Safety Analysis of Linear Hybrid Systems with BDD-Like Data-Structures
IEEE Transactions on Software Engineering
Journal of Embedded Computing - Real-Time and Embedded Computing Systems
TCTL Inevitability Analysis of Dense-Time Systems: From Theory to Engineering
IEEE Transactions on Software Engineering
TCTL inevitability analysis of dense-time systems
CIAA'03 Proceedings of the 8th international conference on Implementation and application of automata
Symbolic model checking of finite precision timed automata
ICTAC'05 Proceedings of the Second international conference on Theoretical Aspects of Computing
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RED (Region Encoding Diagram), first reported in [15], is a BDD-like data-structure for fully symbolic verification of symmetric real-time systems with single clock per process. We propose to extend RED for asymmetric real-time systems with unrestricted number of global or local clocks. Unlike in DBM which records differences between pairs of clock readings, we records the ordering among fractional parts of clock readings into integer sequences encoded in RED's. Like BDD, the new RED is also a minimal canonical form for its target system state-space representations. The number of variables used in RED is O(jXj log jXj) when X is the clock set in the input system description. Experiment has been carried out to compare performance with tools UPPAAL2k and Kronos. Accordingly, we find out that our RED is the most efficient real-time system safety analyzer as long as concurrency complexity is considered.