Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Timing assumptions and verification of finite-state concurrent systems
Proceedings of the international workshop on Automatic verification methods for finite state systems
Automata for modeling real-time systems
Proceedings of the seventeenth international colloquium on Automata, languages and programming
Artificial Intelligence - Special issue on knowledge representation
Symbolic model checking for real-time systems
Information and Computation
Representing and modeling digital circuits
Representing and modeling digital circuits
Real-time symbolic model checking for discrete time models
Theories and experiences for real-time system development
Symbolic model checking of process networks using interval diagram techniques
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Automatic verification of real-time communicating systems by constraint-solving
Proceedings of the 7th IFIP WG6.1 International Conference on Formal Description Techniques VII
The Bounded Retransmission Protocol Must Be on Time!
TACAS '97 Proceedings of the Third International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Formal Design and Analysis of a Gear Controller
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
TACAs '96 Proceedings of the Second International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Efficient Scaling-Invariant Checking of Timed Bisimulation
STACS '97 Proceedings of the 14th Annual Symposium on Theoretical Aspects of Computer Science
Verification of an Audio Control Protocol
ProCoS Proceedings of the Third International Symposium Organized Jointly with the Working Group Provably Correct Systems on Formal Techniques in Real-Time and Fault-Tolerant Systems
Partition Refinement in Real-Time Model Checking
FTRTFT '98 Proceedings of the 5th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
Verification of Real-Time Systems by Successive Over and Under Approximation
Proceedings of the 7th International Conference on Computer Aided Verification
Verification of an Audio Protocol with Bus Collision Using UPPAAL
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Some Progress in the Symbolic Verification of Timed Automata
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Data-Structures for the Verification of Timed Automata
HART '97 Proceedings of the International Workshop on Hybrid and Real-Time Systems
Formal Verification of a TDMA Protocol Start-Up Mechanism
PRFTS '97 Proceedings of the 1997 Pacific Rim International Symposium on Fault-Tolerant Systems
Two examples of verification of multirate timed automata with Kronos
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Compositional and symbolic model-checking of real-time systems
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Approximate reachability analysis of timed automata
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Efficient verification of real-time systems: compact data structure and state-space reduction
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
Formal modeling and analysis of an audio/video protocol: an industrial case study using UPPAAL
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
A User Guide to HyTech
A New Numerical Abstract Domain Based on Difference-Bound Matrices
PADO '01 Proceedings of the Second Symposium on Programs as Data Objects
UPPAAL - Now, Next, and Future
MOVEP '00 Proceedings of the 4th Summer School on Modeling and Verification of Parallel Processes
Verification of Timed Automata via Satisfiability Checking
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
Minimum-Cost Reachability for Priced Timed Automata
HSCC '01 Proceedings of the 4th International Workshop on Hybrid Systems: Computation and Control
Modeling and verification of parallel processes
Higher-Order and Symbolic Computation
Scenario-based timing verification of multiprocessor embedded applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Verification of timed and hybrid systems
ICATPN'00 Proceedings of the 21st international conference on Application and theory of petri nets
Two variables per linear inequality as an abstract domain
LOPSTR'02 Proceedings of the 12th international conference on Logic based program synthesis and transformation
An abstract domain extending difference-bound matrices with disequality constraints
VMCAI'07 Proceedings of the 8th international conference on Verification, model checking, and abstract interpretation
UPPAAL-Tiga: time for playing games!
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Dynamical properties of timed automata revisited
FORMATS'07 Proceedings of the 5th international conference on Formal modeling and analysis of timed systems
BOXES: a symbolic abstract domain of boxes
SAS'10 Proceedings of the 17th international conference on Static analysis
Fully symbolic model checking for timed automata
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Verification, performance analysis and controller synthesis for real-time systems
FSEN'09 Proceedings of the Third IPM international conference on Fundamentals of Software Engineering
Zenoness detection and timed model checking for real time systems
VECoS'07 Proceedings of the First international conference on Verification and Evaluation of Computer and Communication Systems
Proceedings of the tenth ACM international conference on Embedded software
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In this paper, we present Clock Difference Diagrams (CDD), a new BDD-like data-structure for effective representation and manipulation of certain non-convex subsets of the Euclidean space, notably those encountered in verification of timed automata. It is shown that all set-theoretic operations including inclusion checking may be carried out efficiently on Clock Difference Diagrams. Other clock operations needed for fully symbolic analysis of timed automata e.g. future- and reset-operations, can be obtained based on a so-called tight normalform for CDD. A version of the real-time verification tool UPPAAL using Clock Difference Diagrams as the main data-structure has been implemented. Experimental results demonstrate significant space-savings: for nine industrial examples the savings are in average 42% with moderate increase in runtime.