Theoretical Computer Science
Exploiting symmetry in temporal logic model checking
Formal Methods in System Design - Special issue on symmetry in automatic verification
Model Checking of Real-Time Reachability Properties Using Abstractions
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
All from One, One for All: on Model Checking Using Representatives
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
CSL '99 Proceedings of the 13th International Workshop and 8th Annual Conference of the EACSL on Computer Science Logic
Linear Time, Branching Time and Partial Order in Logics and Models for Concurrency, School/Workshop
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Nordic Journal of Computing
Efficient verification of real-time systems: compact data structure and state-space reduction
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
Static Analysis for State-Space Reductions Preserving Temporal Logics
Formal Methods in System Design
Efficient verification of timed automata with BDD-like data structures
International Journal on Software Tools for Technology Transfer (STTT)
MathSAT: Tight Integration of SAT and Mathematical Decision Procedures
Journal of Automated Reasoning
Advanced Unbounded Model Checking Based on AIGs, BDD Sweeping, And Quantifier Scheduling
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Fully Symbolic Timed Model Checking Using Constraint Matrix Diagrams
RTSS '10 Proceedings of the 2010 31st IEEE Real-Time Systems Symposium
A fast linear-arithmetic solver for DPLL(T)
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Exact and fully symbolic verification of linear hybrid automata with large discrete state spaces
Science of Computer Programming
Better Abstractions for Timed Automata
LICS '12 Proceedings of the 2012 27th Annual IEEE/ACM Symposium on Logic in Computer Science
SMT-Based induction methods for timed systems
FORMATS'12 Proceedings of the 10th international conference on Formal Modeling and Analysis of Timed Systems
ACM Computing Surveys (CSUR)
Lazy abstractions for timed automata
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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In this paper we introduce a new formal model, called finite state machines with time (FSMT), to represent real-time systems. We present a model checking algorithm for FSMTs, which works on fully symbolic state sets containing both the clock values and the state variables. In order to verify timed automata (TAs) with our model checking algorithm, we present two different methods to convert TAs to FSMTs. In addition to pure interleaving semantics we can convert TAs to FSMTs having a parallelized interleaving behavior which allows parallelism of transitions causing no conflicts. This can dramatically reduce the number of steps during verification. Our experimental results show that our prototype implementation outperforms the state-of-the-art model checkers UPPAAL and RED.