The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Theoretical Computer Science
Bounded Model Checking for Timed Systems
FORTE '02 Proceedings of the 22nd IFIP WG 6.1 International Conference Houston on Formal Techniques for Networked and Distributed Systems
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
NuSMV 2: An OpenSource Tool for Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Efficient verification of timed automata with BDD-like data structures
International Journal on Software Tools for Technology Transfer (STTT)
Static guard analysis in timed automata verification
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
SAT-based model checking without unrolling
VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
Fully symbolic model checking for timed automata
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Modeling for Symbolic Analysis of Safety Instrumented Systems with Clocks
ACSD '11 Proceedings of the 2011 Eleventh International Conference on Application of Concurrency to System Design
A fast linear-arithmetic solver for DPLL(T)
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
DPLL(T) with exhaustive theory propagation and its application to difference logic
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Fast and flexible difference constraint propagation for DPLL(T)
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
Generalized property directed reachability
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
Beyond lassos: complete SMT-Based bounded model checking for timed automata
FMOODS'12/FORTE'12 Proceedings of the 14th joint IFIP WG 6.1 international conference and Proceedings of the 32nd IFIP WG 6.1 international conference on Formal Techniques for Distributed Systems
| Hi-index | 0.00 |
Modeling time-related aspects is important in many applications of verification methods. For precise results, it is necessary to interpret time as a dense domain, e.g. using timed automata as a formalism, even though the system's resulting infinite state space is challenging for verification methods. Furthermore, fully symbolic treatment of both timing related and non-timing related elements of the state space seems to offer an attractive approach to model checking timed systems with a large amount of non-determinism. This paper presents an SMT-based timed system extension to the IC3 algorithm, a SAT-based novel, highly efficient, complete verification method for untimed systems. Handling of the infinite state spaces of timed system in the extended IC3 algorithm is based on suitably adapting the well-known region abstraction for timed systems. Additionally, k-induction, another symbolic verification method for discrete time systems, is extended in a similar fashion to support timed systems. Both methods are evaluated and experimentally compared to a booleanization-based verification approach that uses the original discrete time IC3 algorithm.