An axiomatic basis for computer programming
Communications of the ACM
Symbolic Model Checking
Automatic Symbolic Verification of Embedded Systems
IEEE Transactions on Software Engineering
Verification of Synchronous Sequential Machines Based on Symbolic Execution
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
The d/dt Tool for Verification of Hybrid Systems
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
Symbolic Parametric Safety Analysis of Linear Hybrid Systems with BDD-Like Data-Structures
IEEE Transactions on Software Engineering
Advanced Unbounded Model Checking Based on AIGs, BDD Sweeping, And Quantifier Scheduling
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Hybridization methods for the analysis of nonlinear systems
Acta Informatica - Hybrid Systems
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
PHAVer: algorithmic verification of hybrid systems past HyTech
International Journal on Software Tools for Technology Transfer (STTT)
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
The image computation problem in hybrid systems model checking
HSCC'07 Proceedings of the 10th international conference on Hybrid systems: computation and control
CAV'07 Proceedings of the 19th international conference on Computer aided verification
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
An AIG-Based QBF-solver using SAT for preprocessing
Proceedings of the 47th Design Automation Conference
Exploiting structure in an AIG based QBF solver
Proceedings of the Conference on Design, Automation and Test in Europe
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
A fast linear-arithmetic solver for DPLL(T)
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
The discrete time behavior of lazy linear hybrid automata
HSCC'05 Proceedings of the 8th international conference on Hybrid Systems: computation and control
PHAVer: algorithmic verification of hybrid systems past hytech
HSCC'05 Proceedings of the 8th international conference on Hybrid Systems: computation and control
Automatic verification of hybrid systems with large discrete state space
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Proceedings of the 14th international conference on Hybrid systems: computation and control
Fully symbolic model checking for timed automata
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Crossing the bridge between similar games
FORMATS'11 Proceedings of the 9th international conference on Formal modeling and analysis of timed systems
Lemma localization: a practical method for downsizing SMT-interpolants
Proceedings of the Conference on Design, Automation and Test in Europe
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We propose an improved symbolic algorithm for the verification of linear hybrid automata with large discrete state spaces (where an explicit representation of discrete states is difficult). Here both the discrete part and the continuous part of the hybrid state space are represented by one symbolic representation called LinAIGs. LinAIGs represent (possibly non-convex) polyhedra extended by Boolean variables. Key components of our method for state space traversal are redundancy elimination and constraint minimization: redundancy elimination eliminates so-called redundant linear constraints from LinAIG representations by a suitable exploitation of the capabilities of SMT (Satisfiability Modulo Theories) solvers. Constraint minimization optimizes polyhedra by exploiting the fact that states already reached in previous steps can be interpreted as ''don't cares'' in the current step. Experimental results (including comparisons to the state-of-the-art model checkers PHAVer and RED) demonstrate the advantages of our approach.