Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A Structure-preserving Clause Form Translation
Journal of Symbolic Computation
Reducing BDD size by exploiting functional dependencies
DAC '93 Proceedings of the 30th international Design Automation Conference
Latch optimization in circuits generated from high-level descriptions
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A Machine-Oriented Logic Based on the Resolution Principle
Journal of the ACM (JACM)
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
SATIRE: a new incremental satisfiability engine
Proceedings of the 38th annual Design Automation Conference
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Exploiting Functional Dependencies in Finite State Machine Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Implicit enumeration of structural changes in circuit optimization
Proceedings of the 41st annual Design Automation Conference
SAT-Based Complete Don't-Care Computation for Network Optimization
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Automatic extraction of functional dependencies
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Interpolant-based transition relation approximation
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Using simulation and satisfiability to compute flexibilities in Boolean networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bi-decomposing large Boolean functions via interpolation and satisfiability solving
Proceedings of the 45th annual Design Automation Conference
Towards automated ECOs in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Scalable don't-care-based logic optimization and resynthesis
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
To SAT or not to SAT: Ashenhurst decomposition in a large scale
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Dependent latch identification in the reachable state space
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
SMT '08/BPR '08 Proceedings of the Joint Workshops of the 6th International Workshop on Satisfiability Modulo Theories and 1st International Workshop on Bit-Precise Reasoning
Invariant-strengthened elimination of dependent state elements
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
Quantifier Elimination via Functional Composition
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Dependent-latch identification in reachable state space
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interpolant generation without constructing resolution graph
Proceedings of the 2009 International Conference on Computer-Aided Design
Interpolating functions from large Boolean relations
Proceedings of the 2009 International Conference on Computer-Aided Design
Iterative layering: optimizing arithmetic circuits by structuring the information flow
Proceedings of the 2009 International Conference on Computer-Aided Design
Learning from Constraints for Formal Property Checking
Journal of Electronic Testing: Theory and Applications
Proceedings of the Conference on Design, Automation and Test in Europe
Scalable liveness checking via property-preserving transformations
Proceedings of the Conference on Design, Automation and Test in Europe
A SAT-based Method for Solving the Two-dimensional Strip Packing Problem
Fundamenta Informaticae - RCRA 2008 Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion
Scalable don't-care-based logic optimization and resynthesis
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Reduction of interpolants for logic synthesis
Proceedings of the International Conference on Computer-Aided Design
A robust functional ECO engine by SAT proof minimization and interpolation techniques
Proceedings of the International Conference on Computer-Aided Design
Exact and fully symbolic verification of linear hybrid automata with large discrete state spaces
Science of Computer Programming
The Synthesis of Cyclic Dependencies with Boolean Satisfiability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Intuitive ECO synthesis for high performance circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Lemma localization: a practical method for downsizing SMT-interpolants
Proceedings of the Conference on Design, Automation and Test in Europe
Computing interpolants without proofs
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
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Functional dependency is concerned with rewriting a Boolean function f as a function h over a set of base functions {g1, ..., gn}, i.e. f = h(g1, ..., gn). It plays an important role in many aspects of electronic design automation (EDA), ranging from logic synthesis to formal verification. Prior approaches to the exploration of functional dependency are based on binary decision diagrams (BDDs), which may not be easily scalable to large designs. This paper proposes a novel reformulation that extensively exploits the capability of modern satisfiability (SAT) solvers. Thereby, functional dependency is detected effectively through incremental SAT solving, and the dependency function h, if it exists, is obtained through Craig interpolation. The main strengths of the proposed approach include: (1) fast detection of functional dependency with modest memory consumption and thus scalable to large designs, (2) a full capacity to handle a large set of base functions and thus discovering dependency whenever exists, and (3) potential application to large-scale logic optimization and verification reduction. Experimental results show the proposed method is far superior to prior work and scales well in dealing with the largest ISCAS89 and ITC99 benchmark circuits with up to 200K gates.