Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Algorithms for approximate FSM traversal
DAC '93 Proceedings of the 30th international Design Automation Conference
Reducing BDD size by exploiting functional dependencies
DAC '93 Proceedings of the 30th international Design Automation Conference
Latch optimization in circuits generated from high-level descriptions
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Approximate reachability with BDDs using overlapping projections
DAC '98 Proceedings of the 35th annual Design Automation Conference
Least fixpoint approximations for reachability analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
SATIRE: a new incremental satisfiability engine
Proceedings of the 38th annual Design Automation Conference
Symbolic Model Checking
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Exploiting Functional Dependencies in Finite State Machine Verification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Implicit enumeration of structural changes in circuit optimization
Proceedings of the 41st annual Design Automation Conference
VERISEC: verifying equivalence of sequential circuits using SAT
HLDVT '05 Proceedings of the High-Level Design Validation and Test Workshop, 2005. on Tenth IEEE International
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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The large number of latches in current digital designs increases the complexity of formal verification and logic synthesis, since an increase in latch numbers leads to an exponential expansion of the state space. One solution to this problem is to find the functional dependences among these latches. With the information of functional dependences, these latches can be identified as dependent or essential latches, and the state space can be constructed using only the essential latches. Although much research has been devoted to exploring the functional dependences among latches using binary-decision-diagram (BDD)-based symbolic algorithms, this issue is still unresolved for large sequential circuits. In this paper, we propose a heuristic to identify the dependent latches based on the state-of-the-art work. In addition, our proposed approach detects sequential functional dependences existing in the reachable state space only. The sequential functional dependences can identify additional dependent latches after a specific time frame in order to achieve additional reduction of the state space. Experimental results show that this approach can deal with large sequential circuits with up to 9000 latches in a reasonable time while simultaneously identifying their combinational and sequential dependent latches. For instance, with s13207 in ISCAS'89, 23% of the latches are identified as combinational dependent latches, and an additional 13% of the latches are identified as sequential dependent latches. For the reachability analysis of s13207, with the benefits of dependent-latch identification, 70.70% of the BDD size and 73.32% of the CPU time can be reduced within the same time frame. Furthermore, 2890.76% more states can be reached under the 600 000-s run-time limit.