Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Solving the incremental satisfiability problem
Journal of Logic Programming
New ideas for solving covering problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Functional test generation for delay faults in combinational circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
ATPG tools for delay faults at the functional level
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On applying incremental satisfiability to delay fault testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A machine program for theorem-proving
Communications of the ACM
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
A Tutorial on Stålmarcks's Proof Procedure for Propositional Logic
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Monitor-Based Formal Specification of PCI
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
An Incremental Branch-And-Bound Method for the Satisfiability Problem
INFORMS Journal on Computing
On Solving Stack-Based Incremental Satisfiability Problems
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
The propositional formula checker HeerHugo
The propositional formula checker HeerHugo
Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1,2
Proceedings of the 2002 international symposium on Low power electronics and design
Robust SAT-Based Search Algorithm for Leakage Power Reduction
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Generic ILP versus specialized 0-1 ILP: an update
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Inference methods for a pseudo-boolean satisfiability solver
Eighteenth national conference on Artificial intelligence
Leakage current reduction in CMOS VLSI circuits by input vector control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AMUSE: a minimally-unsatisfiable subformula extractor
Proceedings of the 41st annual Design Automation Conference
Refining the SAT decision ordering for bounded model checking
Proceedings of the 41st annual Design Automation Conference
On SAT Instance Classes and a Method for Reliable Performance Experiments with SAT Solvers
Annals of Mathematics and Artificial Intelligence
Beyond safety: customized SAT-based model checking
Proceedings of the 42nd annual Design Automation Conference
Generalizing symbolic execution to library classes
PASTE '05 Proceedings of the 6th ACM SIGPLAN-SIGSOFT workshop on Program analysis for software tools and engineering
Incremental deductive & inductive reasoning for SAT-based bounded model checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
On the relation between simulation-based and SAT-based diagnosis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Automatic Debugging of Real-Time Systems Based on Incremental Satisfiability Counting
IEEE Transactions on Computers
Accelerating high-level bounded model checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Stochastic local search for incremental SAT
International Journal of Knowledge-based and Intelligent Engineering Systems
HySAT: An efficient proof engine for bounded model checking of hybrid systems
Formal Methods in System Design
A new hybrid solution to boost SAT solver performance
Proceedings of the conference on Design, automation and test in Europe
On-the-fly resolve trace minimization
Proceedings of the 44th annual Design Automation Conference
Using SAT-based techniques in power estimation
Microelectronics Journal
Boosting interpolation with dynamic localized abstraction and redundancy removal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Solution and Optimization of Systems of Pseudo-Boolean Constraints
IEEE Transactions on Computers
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Using unsatisfiable cores to debug multiple design errors
Proceedings of the 18th ACM Great Lakes symposium on VLSI
CADE-21 Proceedings of the 21st international conference on Automated Deduction: Automated Deduction
An approach for extracting a small unsatisfiable core
Formal Methods in System Design
Dependent latch identification in the reachable state space
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Functional test generation using design and property decomposition techniques
ACM Transactions on Embedded Computing Systems (TECS)
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
Computing bounds for fault tolerance using formal techniques
Proceedings of the 46th Annual Design Automation Conference
Dependent-latch identification in reachable state space
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Incremental Algorithm to Check Satisfiability for Bounded Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Efficient Proof Engines for Bounded Model Checking of Hybrid Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
Automatic fault localization for property checking
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
Combining abstraction refinement and SAT-based model checking
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
RobuCheck: a robustness checker for digital circuits
Proceedings of the First Workshop on DYnamic Aspects in DEpendability Models for Fault-Tolerant Systems
Functional test generation using efficient property clustering and learning techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An AIG-Based QBF-solver using SAT for preprocessing
Proceedings of the 47th Design Automation Conference
Range and Set Abstraction using SAT
Electronic Notes in Theoretical Computer Science (ENTCS)
A SAT-based Method for Solving the Two-dimensional Strip Packing Problem
Fundamenta Informaticae - RCRA 2008 Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion
Approximate quantifier elimination for propositional boolean formulae
NFM'11 Proceedings of the Third international conference on NASA Formal methods
Applying SMT in symbolic execution of microcode
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Incremental compilation-to-SAT procedures
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Incremental and complete bounded model checking for full PLTL
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
An analysis of SAT-based model checking techniques in an industrial environment
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Simultaneous SAT-Based model checking of safety properties
HVC'05 Proceedings of the First Haifa international conference on Hardware and Software Verification and Testing
Directed test generation for validation of multicore architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Efficient SAT solving under assumptions
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
Preprocessing in incremental SAT
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
Gearing up for effective ASP planning
Correct Reasoning
Implicative simultaneous satisfiability and applications
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
Asynchronous multi-core incremental SAT solving
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
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We introduce SATIRE, a new satisfiability solver that is particular-ly suited to verification and optimization problems in electronic de-sign automation. SATIRE builds on the most recent advances in satisfiability research, and includes two new features to achieve even higher performance: a facility for incrementally solving sets of related problems, and the ability to handle non-CNF constraints. We provide experimental evidence showing the effectiveness of these additions to classical satisfiability solvers.