Symbolic execution and program testing
Communications of the ACM
SATIRE: a new incremental satisfiability engine
Proceedings of the 38th annual Design Automation Conference
Pruning Techniques for the SAT-Based Bounded Model Checking Problem
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Robust Search Algorithms for Test Pattern Generation
FTCS '97 Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97)
Embedded Software Validation: Applying Formal Techniques for Coverage and Test Generation
MTV '06 Proceedings of the Seventh International Workshop on Microprocessor Test and Verification
Efficient symbolic simulation of low level software
Proceedings of the conference on Design, automation and test in Europe
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Handbook of Satisfiability: Volume 185 Frontiers in Artificial Intelligence and Applications
Handbook of Satisfiability: Volume 185 Frontiers in Artificial Intelligence and Applications
Predicting learnt clauses quality in modern SAT solvers
IJCAI'09 Proceedings of the 21st international jont conference on Artifical intelligence
Approximating the safely reusable set of learned facts
International Journal on Software Tools for Technology Transfer (STTT) - Special Section on HVC 07
A scalable decision procedure for fixed-width bit-vectors
Proceedings of the 2009 International Conference on Computer-Aided Design
Generalized symbolic execution for model checking and testing
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
A lazy and layered SMT(BV) solver for hard industrial verification problems
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Formal verification of backward compatibility of microcode
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Acceleration of SAT-based iterative property checking
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Simultaneous SAT-Based model checking of safety properties
HVC'05 Proceedings of the First Haifa international conference on Hardware and Software Verification and Testing
Satisfiability modulo recursive programs
SAS'11 Proceedings of the 18th international conference on Static analysis
Effective word-level interpolation for software verification
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Efficient SAT solving under assumptions
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
Preprocessing in incremental SAT
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
Solving temporal problems using SMT: strong controllability
CP'12 Proceedings of the 18th international conference on Principles and Practice of Constraint Programming
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
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Microcode is a critical component in modern microprocessors, and substantial effort has been devoted in the past to verify its correctness. A prominent approach, based on symbolic execution, traditionally relies on the use of boolean SAT solvers as a backend engine. In this paper, we investigate the application of Satisfiability Modulo Theories (SMT) to the problem of microcode verification. We integrate MathSAT, an SMT solver for the theory of Bit Vectors, within the flow of microcode verification, and experimentally evaluate the effectiveness of some optimizations. The results demonstrate the potential of SMT technologies over pure boolean SAT.