Record & play: a structural fixed point iteration for sequential circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Deriving Logic Systems for Path Delay Test Generation
IEEE Transactions on Computers
Combinational equivalence checking using satisfiability and recursive learning
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Algorithms for solving Boolean satisfiability in combinational circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Boolean satisfiability in electronic design automation
Proceedings of the 37th Annual Design Automation Conference
Constructive library-aware synthesis using symmetries
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Using SAT for combinational equivalence checking
Proceedings of the conference on Design, automation and test in Europe
Generalized reasoning scheme for redundancy addition and removal logic optimization
Proceedings of the conference on Design, automation and test in Europe
Functional extension of structural logic optimization techniques
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
SATIRE: a new incremental satisfiability engine
Proceedings of the 38th annual Design Automation Conference
Accelerating boolean satisfiability through application specific processing
Proceedings of the 14th international symposium on Systems synthesis
Logic Synthesis and Verification
SAT and ATPG: algorithms for Boolean decision problems
Logic Synthesis and Verification
An Overview of Backtrack Search Satisfiability Algorithms
Annals of Mathematics and Artificial Intelligence
Verification of integer multipliers on the arithmetic bit level
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Resynthesis of multi-level circuits under tight constraints using symbolic optimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
9.2 On Delay-Untestable Paths and Stuck-Fault Redundancy
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Solving Satisfiability in Combinational Circuits
IEEE Design & Test
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints
IEEE Transactions on Computers
GridSAT: a system for solving satisfiability problems using a computational grid
Parallel Computing - Optimization on grids - Optimization for grids
Improving constant-coefficient multiplier verification by partial product identification
Proceedings of the conference on Design, automation and test in Europe
Representing Logical Inference Steps with Digital Circuits
Proceedings of the Symposium on Human Interface 2009 on Human Interface and the Management of Information. Information and Interaction. Part II: Held as part of HCI International 2009
Nenofex: expanding NNF for QBF solving
SAT'08 Proceedings of the 11th international conference on Theory and applications of satisfiability testing
Solving satisfiability in combinational circuits with backtrack search and recursive learning
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
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