Uncertainty, Energy, and Multiple-Valued Logics
IEEE Transactions on Computers
Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
The optimistic update theorem for path delay testing in sequential circuits
Journal of Electronic Testing: Theory and Applications
Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Testing for path delay faults in synchronous digital circuits
Testing for path delay faults in synchronous digital circuits
A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits
IEEE Transactions on Computers
Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
A rated-clock test method for path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Introduction To Automata Theory, Languages, And Computation
Introduction To Automata Theory, Languages, And Computation
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Generation of Compact Delay Tests by Multiple-Path Activation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Generation of high quality tests for functional sensitizable paths
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
New techniques to verify timing correctness of integrated circuits
New techniques to verify timing correctness of integrated circuits
On variable clock methods for path delay testing of sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Generalized Sensitization using Fault Tuples
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
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We present an algorithm to derive logic systems for various classes of path delay test problems. In these logic systems, the value of a signal represents the relevant conditions that occur during a set of consecutively applied vectors. Starting from a set of basic values for valid signals at primary inputs, a state transition graph is constructed to enumerate all possible signal states relevant to path activation that are reachable by Boolean operations. These states include all incompletely specified states, composed as combinations of basic values. A distinguishability analysis then finds all state-pairs that need to be distinguished during test generation. The final step minimizes the number of states. For forward and backward implications of test generation in combinational or sequential circuits, the procedure provides optimal logic systems. We define optimality as the smallest set of logic states that provides the least possible ambiguity in implications. Thus, an optimal set of logic states will minimize the number of backtracks in test generation. A 10-valued logic described in the literature is found to be optimal for generating tests for single path delay faults. Other problems addressed in this paper include compact test generation through activation of many single path delay faults, test generation for rated-clock test application, and test generation for multiple path delay faults. The limitations and capabilities of various logic systems are illustrated by examples.