Deriving Logic Systems for Path Delay Test Generation
IEEE Transactions on Computers
A non-enumerative path delay fault simulator for sequential circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Delay Fault Testing of Designs with Embedded IP Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Path-Delay Fault Diagnosis in Non-Scan Sequential Circuits with At-Speed Test Application
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Implicit and Exact Path Delay Fault Grading in Sequential Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A Probabilistic Approach to Diagnose SETs in Sequential Circuits
Journal of Electronic Testing: Theory and Applications
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We propose a delay test methodology for general sequential circuits. To test a combinational path between two flip-flops, the source flip-flop is initialized to the appropriate value, followed by creation of a transition, which is propagated through the path. An incorrect logic value is captured in the destination flip-flop if the path delay exceeds the clock period. The state of the destination flip-flop is observed at a primary output through path sensitization. Only one vector that propagates the transition through the path is applied with the rated clock period. All other vectors use a slow speed clock to ensure fault-free initialization and fault effect observation. The test generation method uses a 13-value algebra that represents the relevant transition and hazard states of signals. Since several path delay faults can be activated by the vector applied at the rated clock, only the flip-flops with hazard-free steady values are assumed to have deterministic states. This allows us to generate sequentially robust tests. We present the results of the test generation method on ISCAS benchmark circuits