Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
At-speed delay testing of synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
ATPG for Path Delay Faults without Path Enumeration
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults
Proceedings of the conference on Design, automation and test in Europe - Volume 1
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On variable clock methods for path delay testing of sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The path-status graph with application to delay fault simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Identification of primitive faults in combinational and sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact path delay fault coverage with fundamental ZBDD operations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The first path implicit and exact non-robust path delay fault grading technique for non-scan sequential circuits is presented. Non enumerative exact coverage is obtained, by allowing any latched error representing a delayed transition to propagate to a primary output with thesupport of other potentially latched errors. The generalized error propagation is done by symbolic simulation. Appropriate data structures for function manipulation are used. The advantage of the proposed method is demonstrated experimentally with consistent improvement in coverage over an existing pessimistic heuristic despite enforced bounds onthe memory requirements.