A BIST Approach for Very Deep Sub-Micron (VDSM) Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit?
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Low power ATPG for path delay faults
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Implicit and Exact Path Delay Fault Grading in Sequential Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Implicit grading of multiple path delay faults
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Techniques to prioritize paths for diagnosis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present an efficient path-delay fault (PDF) simulator that does not involve the enumeration of paths. Our method calculates the exact fault coverage, and identifies all tested faults in any circuit with a large number of paths. We present a new data structure, called the path-status graph (PSG), to efficiently hold the status of each PDF in the circuit, i.e., whether or not the PDF is tested. The keg to this efficiency is in breaking the information into pieces and distributing it over the data structure, and in retaining all or part of the reconverging fan-out structure of the circuit in the PSG. Thus, an exponential number of PDF's can share the same piece of information. Using 1000 random tests, we simulated all of the approximately 1020 PDF's in the circuit c6288, and determined that 4.4 billion faults were detected. This number is larger by over three orders of magnitude compared to what was possible with previously reported methods