Low power ATPG for path delay faults

Authors:
M.M Vaseekar Kumar;S. Padmanaban;S. Tragoudas
Affiliations:
Southern Illinois University, Carbondale, Carbondale, IL;University of Maryland, Baltimore County, Baltimore, MD;Southern Illinois University, Carbondale, Carbondale, IL
Venue:
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Year:
2004

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Abstract

In this paper we propose an implicit test pattern generation method so that many path delay faults are covered and the dissipated power satisfies a given bound. Typical delay values are considered from an accurate gate delay model. We use a timed ATPG that combines function-based and structural (PODEM-like) methods for faster test generation, which is also more accurate in sequential circuits.