Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
RESIST: a recursive test pattern generation algorithm for path delay faults
EURO-DAC '94 Proceedings of the conference on European design automation
BiTeS: a BDD based test pattern generator for strong robust path delay faults
EURO-DAC '94 Proceedings of the conference on European design automation
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Accurate Path Delay Fault Coverage is Feasible
ITC '99 Proceedings of the 1999 IEEE International Test Conference
NEST: a nonenumerative test generation method for path delay faults in combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast nonenumerative automatic test pattern generator for path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact Path Delay Grading with Fundamental BDD Operations
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Low power ATPG for path delay faults
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Non-Enumerative Path Delay Fault Diagnosis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Implicit deductive fault simulation for complex delay fault models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implicit and Exact Path Delay Fault Grading in Sequential Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Low power test generation for path delay faults using stability functions
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Function-based compact test pattern generation for path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a new ATPG methodology for detecting path delay faults in combinational circuits. The proposed approach is non-enumerative and generates a small number of test patterns with high fault coverage. A new ATPG framework for path delay faults is introduced; it collapses the two phases (path sensitization and line justification) of traditional ATPGs into one. The proposed framework utilizes both structural and functional techniques. A BDD-based implementation and experimentation with the ISCAS'85 benchmarks shows that the proposed method outperforms all ATPG methods that bound the test set. The results also show that the approach is comparable to existing ATPG methods that do not bound the test set.