Path delay fault testing using test points
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ATPG for Path Delay Faults without Path Enumeration
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation
Journal of Electronic Testing: Theory and Applications
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Journal of Electronic Testing: Theory and Applications
Function-based compact test pattern generation for path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a nonenumerative automatic test pattern generator for robustly testable path delay faults. In contrast to earlier work by I. Pomeranz, et al. (see IEEE Trans. Computer-Aided Design, vol. 14, p. 1505-15, Dec. 1995), the pattern generator takes into consideration the conditions for robust propagation while sensitizing sets of paths. This increases the probability of testing them robustly with a single test. Novel algorithms are described which identify sets that contain many such potentially compatible paths. The number of detected faults is estimated using a simple and fast method. The approach compares favorably to that of Pomeranz et al. in both fault detection and time performance