Delay fault test generation for scan/hold circuits using Boolean expressions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
RESIST: a recursive test pattern generation algorithm for path delay faults
EURO-DAC '94 Proceedings of the conference on European design automation
BiTeS: a BDD based test pattern generator for strong robust path delay faults
EURO-DAC '94 Proceedings of the conference on European design automation
A satisfiability-based test generator for path delay faults in combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Testing for Path Delay Faults Using Test Points
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Identification and Test Generation for Primitive Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
Efficient Identification of Non-Robustly Untestable Path Delay Faults
Proceedings of the IEEE International Test Conference
Generation of Compact Delay Tests by Multiple-Path Activation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
NEST: a nonenumerative test generation method for path delay faults in combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design-for-testability for path delay faults in large combinational circuits using test points
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast nonenumerative automatic test pattern generator for path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Inserting controllable/observable points in the test architecture has been shown to be a viable method for reducing the number of path delay faults that need to be tested in a circuit. In order to have a minimal impact on the operation clock and more accuracy in testing, it is proposed that test points should be inserted with the additional constraint that every path has a bounded number of test points. A polynomial time solvable integer linear programming (ILP) formulation serves as the basis for the presented test placement methodology. Due to the ILP's global optimization property we achieve results that are comparable to those by an existing greedy technique for the less constrained test point placement problem.