Testing for Path Delay Faults Using Test Points

Authors:
Spyros Tragoudas;N. Denny
Affiliations:
-;-
Venue:
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Year:
1999

Citing 0
Cited 3

Path delay fault testing using test points

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Exact Path Delay Grading with Fundamental BDD Operations

ITC '01 Proceedings of the 2001 IEEE International Test Conference
Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors

Journal of Electronic Testing: Theory and Applications

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Abstract

Path delay fault testing is often difficult due to the large number of paths that must be tested. Inserting controllable/observable points in the test architecture has been shown to be a viable method for reducing the number of paths that need to be tested in a circuit. Test points allow the tester to test sub-paths of the circuit and then draw conclusions of the operability of the circuit based upon the delays of sub-paths.We illustrate some of the limitations of current sub-path testing procedures and illustrate some of the difficulties associated with unstructured test point placement. We give an implementation of test points embedded in a schan chain and present a new testing technique that is more accurate than the previous method. We also present a novel test point insertion approach that has reasonable test times and minimal impact on the hardware size and the operational clock.