Generation of Compact Delay Tests by Multiple-Path Activation

Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Deriving Logic Systems for Path Delay Test Generation

IEEE Transactions on Computers

Path delay fault testing using test points

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Static compaction for two-pattern test sets

ATS '95 Proceedings of the 4th Asian Test Symposium

Functional test generation for path delay faults

ATS '95 Proceedings of the 4th Asian Test Symposium

Sequential logic path delay test generation by symbolic analysis

ATS '95 Proceedings of the 4th Asian Test Symposium

An efficient automatic test generation system for path delay faults in combinational circuits

VLSID '95 Proceedings of the 8th International Conference on VLSI Design

Diagnosis of parametric path delay faults

VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication

Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

20.1 A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

Algorithms for Switch Level Delay Fault Simulation

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Dynamic Test Compaction for Bridging Faults

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Path delay test compaction with process variation tolerance

Proceedings of the 42nd annual Design Automation Conference

A dynamic test compaction procedure for high-quality path delay testing

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation

Journal of Electronic Testing: Theory and Applications

Switching activity as a test compaction heuristic for transition faults

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Function-based compact test pattern generation for path delay faults

IEEE Transactions on Very Large Scale Integration (VLSI) Systems