IEEE Transactions on Computers
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Generation of Compact Delay Tests by Multiple-Path Activation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
An Introduction to Switch-Level Modeling
IEEE Design & Test
A Survey of Switch-Level Algorithms
IEEE Design & Test
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
SWiTEST: a switch level test generation system for CMOS combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Delay test problems are well understood for gate levelcircuits. -For certain logic families, delays depend onthe charge stored at internal nodes. For such circuits,gate level models do not sufice. A switch level simulatorcan be used for logic verification and stuck-at faultsimulation. Toward making the delay fault simulationpossible, this paper contributes three innovations to theswitch-level technique: (1) Signals that remain steadyover two consecutive vectors are identified using additionalstrength designations for charge and dischargepaths; (2) Delay faults are propagated through MOSgates using articulation analysis of the graph; and (3)A modified relaxation procedure determines the steadyor non-steady status of signals at the same time it evaluatesnodes. Experimental results demonstrate the validityof algorithms.