Algorithms for Switch Level Delay Fault Simulation
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Critical Path Identification and Delay Tests of Dynamic Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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Switch-level modeling is a recently developed design and analysis methodology for MOS VLSI circuits. At the switch level,important features of MOS circuits can be directly modeled using a moderate number of discrete parameters, including switchstates, resistance, capacitance, and bidirectional signals. Switch-level models, provide more accurate behavioral and structuralinformation than gate-level logical models, while avoiding the high computational cost associated with analog electrical models.