Algorithms for Switch Level Delay Fault Simulation
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Critical Path Identification and Delay Tests of Dynamic Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A new modeling technique for mixed-mode simulation of CMOS circuits
Integration, the VLSI Journal
Verification of the power-down mode of analog circuits by structural voltage propagation
Analog Integrated Circuits and Signal Processing
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits
Journal of Electronic Testing: Theory and Applications
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The switch-level model provides a logical abstraction from the physical structure of a metal-oxide semiconductor(MOS) circuitto its digital behavior. At the switch level, a circuit is modeled as a network of transistor switches connecting a set ofcharge storage nodes. Node voltages are represented by discrete logic levels, and electrical behavior is modeled in a highlysimplified way. Switch-level algorithms have been applied to such tasks as logic and fault simulation, formal hardware verification,timing analysis, and automatic test program generation. They have been implemented on sequential and parallel computers aswell as by hardware simulation accelerators.