Computer aids for VLSI design
Design methodologies and CAD tools
Integration, the VLSI Journal
Massive parallelism in multi-level simulation of VLSI circuits
Integration, the VLSI Journal
Mixed-Mode Simulation and Analog Multilevel Simulation
Mixed-Mode Simulation and Analog Multilevel Simulation
Mixed-Mode Simulation
A Survey of Switch-Level Algorithms
IEEE Design & Test
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
Partitioning and ordering of CMOS circuits for switch level analysis
Integration, the VLSI Journal
Switch-level timing simulation of bipolar ECL circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electrical-logic simulation and its applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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An efficient and accurate simulation of digital circuits is of utmost importance in VLSI design to correctly predict timing performance and to accurately predict electrical waveform at all the nodes which link to analog blocks. To achieve this objective, an improved technique to correctly model the conductance of MOS device for electrical logic simulation (ELogic) of CMOS circuits is proposed [7]. The technique is general and applicable to any integrable analytic device current model. The model is implemented in a well-known mixed-mode simulator iSPLICE3. The examples show that the improved technique is able to correctly predict several complete electrical waveforms with a large voltage step of 1 V with only five logic levels to yield at least an order of magnitude computational time advantage over the circuit simulation with virtually minimal loss in the accuracy.