Algorithms
A Survey of Switch-Level Algorithms
IEEE Design & Test
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
Switch-level simulation using dynamic graph algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, a new method for the verification of the power-down mode of analog circuits is presented. In power-down mode, internal nodes of the circuit can be floating. These nodes can cause short-circuit paths and reliability problems due to stress. However, automatic and reliable detection of floating nodes is not straightforward, because numerical simulation is often not trustworthy in the presence of floating nodes. The presented method estimates the node voltages in power-down mode by using a voltage propagation approach based on the circuit structure. No numerical simulation is needed. The circuit is transformed to a propagation graph which models the static behavior of the circuit. The propagation graph is scanned for short-circuit paths. Experimental results demonstrate the effectiveness and efficiency of the presented method as well as common pitfalls of numerical simulation.