Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
IEEE Transactions on Computers
Automatic generation of behavioral models from switch-level descriptions
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Analysis of switch-level faults by symbolic simulation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Extracting RTL models from transistor netlists
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Combinational equivalence checking using satisfiability and recursive learning
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Digital MOS circuit partitioning with symbolic modeling
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Transistor level test generation for MOS circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
SLS—a fast switch level simulator for verification and fault coverage analysis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Circuit-based Boolean Reasoning
Proceedings of the 38th annual Design Automation Conference
Beyond the Byzantine Generals: Unexpected Behaviour and Bridging Fault Diagnosis
Proceedings of the IEEE International Test Conference on Test and Design Validity
ITC '98 Proceedings of the 1998 IEEE International Test Conference
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Testing for bridging faults (shorts) in CMOS circuits
DAC '83 Proceedings of the 20th Design Automation Conference
Razor: A Tool for Post-Silicon Scan ATPG Pattern Debug and Its Application
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Design for Manufacturability and Statistical Design: A Comprehensive Approach
Design for Manufacturability and Statistical Design: A Comprehensive Approach
A Survey of Switch-Level Algorithms
IEEE Design & Test
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
How Many Test Vectors We Need to Detect a Bridging Fault?
Journal of Electronic Testing: Theory and Applications
Test Pattern Generation using Boolean Proof Engines
Test Pattern Generation using Boolean Proof Engines
Extraction error modeling and automated model debugging in high-performance custom designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Algorithms for an Advanced Fault Simulation System in MOTIS
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Experimental Characterization of CMOS Interconnect Open Defects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On Acceleration of SAT-Based ATPG for Industrial Designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SWiTEST: a switch level test generation system for CMOS combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This work extends to the switch level the verification and testing techniques based upon boolean satisfiability (SAT), so that SAT-based methodologies can be applied to circuits that cannot be well described at the gate level. The main achieved goal was to define a boolean model describing switch-level circuit operations as a SAT problem instance, to be applied to combinational equivalence checking and bridging-fault test generation. Results are provided for a set of combinational CMOS circuits, showing the feasibility of SAT-based verification and testing of switch-level circuits.