Transistor level test generation for MOS circuits

Authors:
Madhukar K. Reddy;Sudhakar M. Reddy;Prathima Agrawal
Affiliations:
Department of Electrical and Computer Engineering, University of Iowa, Iowa City, Iowa;-;AT&T Bell Telephone Laboratories, 600 Mountain Avenue, Murray Hill, New Jersey
Venue:
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Year:
1985

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Abstract

Due to inaccuracies in gate level models of VLSI digital circuits, current practice is to use transistor level simulators to analyze VLSI digital circuits. The inaccuracies of gate level models are even more severe when faults in digital circuits are considered. For this reason, recently several researchers have proposed the use of test pattern generation from digital circuits described at the transistor level. In this paper an efficient test pattern generation procedure for digital circuits described at the transistor level is given.