Transistor level test generation for MOS circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Transistor-level test generation for physical failures in CMOS circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
On fault detection in CMOS logic networks
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
A fault simulation methodology for VLSI
DAC '82 Proceedings of the 19th Design Automation Conference
Modeling and Test Generation Algorithms for MOS Circuits
IEEE Transactions on Computers
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The aim of this paper is to specify a fault simulation and test pattern generation environment, which includes a multiple-valued algebra, allows the natural treatment of loops and bidirectional devices, and models the physical failures. The main idea of this work is to define what is possible when no extraction to gate level and no creation of transistor groups are performed.