A gate level model for CMOS combinational logic circuits with application to fault detection

Authors:
Sudhakar M. Reddy;Vishwani D. Agrawal;Sunil K. Jain
Affiliations:
Department of Electrical and Computer Engineering, University of Iowa, Iowa City, Iowa;AT&T Bell Laboratories, Murray Hill, New Jersey;AT&T Bell Laboratories, Murray Hill, New Jersey
Venue:
DAC '84 Proceedings of the 21st Design Automation Conference
Year:
1984

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Abstract

A procedure to derive gate level equivalent circuits for CMOS combinational logic circuits is given. The procedure leads to a model containing AND, OR and NOT gates. Specifically it does not require memory elements as does an earlier model and also uses fewer gates. It is shown that tests for classical stuck-at-0 and stuck-at-1 faults in the equivalent circuit can be used to detect line stuck-at, stuck-open and stuck-on faults in the modeled CMOS circuit.