A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits
IEEE Transactions on Computers
Multiple Stuck-Open Fault Detection in CMOS Logic Circuits
IEEE Transactions on Computers - Fault-Tolerant Computing
Test generation of stuck-open faults using stuck-at test sets in CMOS combinational circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A new approach to derive robust sets for stuck-open faults in CMOS combinational logic circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A method of delay fault test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
On fault detection in CMOS logic networks
DAC '83 Proceedings of the 20th Design Automation Conference
A gate level model for CMOS combinational logic circuits with application to fault detection
DAC '84 Proceedings of the 21st Design Automation Conference
Deception by Design: Fooling Ourselves with Gate-level Models
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Testing for Resistive Opens and Stuck Opens
ITC '01 Proceedings of the 2001 IEEE International Test Conference
EURO-DAC '90 Proceedings of the conference on European design automation
EURO-DAC '90 Proceedings of the conference on European design automation
A CMOS LSSD test generation system
IBM Journal of Research and Development
Stuck-open and transition fault testing in CMOS complex gates
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On CMOS totally self-checking circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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Because of its relative low power dissipation, intermediate speed, and high density, CMOS (Complementary Metal Oxide Semiconductor) will emerge as one of the leading VLSI technologies. Therefore, testing CMOS VLSI circuits is very important. The conventional stuck-at fault assumptions are not sufficient for modeling some faults that are peculiar to CMOS circuitry, specifically the stuck-open faults. These faults are sequential in nature. This means that when a fault occurs in a combinational circuits, the circuit behaves as a sequential circuit. Therefore, special test pattern generation techniques are necessary to test this type of faults. In this paper, we present an algorithm which uses the conventional stuck-at list to detect some stuck-open faults. Some modifications of the conventional testing procedure are necessary. Such modifications and their associated programming effort are expected to be straight forward. For the stuck-open faults that cannot be detected by the conventional stuck-at test list, a second algorithm is descirbed that generates the tests for such faults. The algorithm generates the test if such a test exists. If not, the fault is declared as undetectable. First, we will discuss the stuck-open fault and its peculiarity to CMOS circuitry. Second, we will describe the step-by-step algorithms used to generate a complete test list for this type of fault. Finally, a small example circuit will be used to illustrate the new test generation technique and some conclusive remarks will be given.