A CMOS LSSD test generation system

Authors:
D. Leet;P. Shearon;R. France
Affiliations:
IBM General Technology Division, Burlington facility, P.O. Box A, Essex Junction, Vermont;IBM General Technology Division, P.O. Box 6, Endicott, New York;IBM General Technology Division, P.O. Box 6, Endicott, New York
Venue:
IBM Journal of Research and Development
Year:
1984

Citing 3
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Abstract

Automatic test pattern generators based on the stuck-fault concept are theoretically inadequate in their ability to generate test patterns for CMOS circuits. A new set of pin faults, called CMOS faults, is discussed that can represent the necessary test pattern sequences for these circuits. Processing of these faults by a new test pattern generator, called the Enhanced Test Generator (ETG), is also described.