Evaluation of a fan out stem based fault simulation in sequential circuits

Authors:
Frederick J. Hill;Eltayeb S. Abuelyaman
Affiliations:
Department of Electrical and Computer Engineering University of Arizona Tucson, AZ 85721, USA;Department of Electrical Engineering Western Michigan University Kalamazoo, MI 49008, USA
Venue:
Mathematical and Computer Modelling: An International Journal
Year:
1990

Citing 8
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Abstract

This paper develops a new algorithm for fault simulation in sequential circuits. Surrogate fault simulation extracts faults from combinational logic and propagates stored faults. Estimates indicate that the one period execution time for all critical steps varies with the first power of the number of gates as opposed to the second power as does a parallel fault simulation.