On computing optimized input probabilities for random tests
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A method for generating weighted random test pattern
IBM Journal of Research and Development
Analysis of timing failures due to random AC defects in VLSI modules
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A delay test system for high speed logic LSI's
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
A CMOS LSSD test generation system
IBM Journal of Research and Development
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
An Experimental Delay Test Generator for LSI Logic
IEEE Transactions on Computers
Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks
IEEE Transactions on Computers
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
The Effects of Races, Delays, and Delay Faults on Test Generation
IEEE Transactions on Computers
A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits
IEEE Transactions on Computers
Delay test effectiveness evaluation of LSSD-based VLSI logic circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A Test Methodology for High Performance MCMs
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
| Hi-index | 0.00 |