Algorithms for Detection of Faults in Logic Circuits
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
A method for generating weighted random test pattern
IBM Journal of Research and Development
A logic chip delay-test method based on system timing
IBM Journal of Research and Development
Cellular automata circuits for built-in self test
IBM Journal of Research and Development
10.3 Distributed Generation of Weighted Random Patterns
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Hardware Ef.cient LBISTWith Complementary Weights
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Design for Testability A Survey
IEEE Transactions on Computers
Efficiency of Random Compact Testing
IEEE Transactions on Computers
IEEE Transactions on Computers
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A heuristic test-pattern generator for programmable logic arrays
IBM Journal of Research and Development
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
Design of an efficient weighteld random pattern generation system
ITC'94 Proceedings of the 1994 international conference on Test
Fault detection effectiveness of weighted random patterns
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
WTPGA: a novel weighted test-pattern generation approach for VLSI built-in self test
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Synthesis and optimization procedures for fully and easily testable sequential machines
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
An incomplete scan design approach to test generation for sequential machines
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Sufficient testing in a self-testing environment
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
The coverage problem for random testing
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
LSI logic testing: an overview
IEEE Transactions on Computers
On methods to match a test pattern generator to a circuit-under-test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Random test generation with input cube avoidance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Electronic Testing: Theory and Applications
Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints
Journal of Electronic Testing: Theory and Applications
| Hi-index | 14.99 |
A heuristic method for generating large-scale integration (LSI) test patterns is described. In particular, this paper presents a technique for generating statistically random sequences to test complex logic circuits. The algorithms used to obtain a set of tests by means of weighted logic signal variations are included. Several techniques for assigning these weights and for varying them are discussed on the basis of the primary algorithm. Also described is a means of obtaining a minimal number of test patterns. This approach has proved successful in obtaining fault-detecting patterns.