RTG: automatic register level test generator
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
EBT: A comprehensive test generation technique for highly sequential circuits
DAC '78 Proceedings of the 15th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits
IEEE Transactions on Computers
A comprehensive approach to the partial scan problem using implicit state enumeration
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Partial Scan Using Multi-Hop State Reachability Analysis
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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In this paper, we present an Incomplete Scan Design approach to sequential test generation. This approach represents a significant departure from previous methods. First, using an efficient sequential testing algorithm, test sequences are generated for a large number of possible faults in the given sequential circuit. A minimal subset of memory elements is then found, which if made observable and controllable will result in easy detection of the sequentially redundant and irredundant but difficult-to-detect faults. The deterministic test generation algorithm is again used to generate tests for these faults in the modified circuit ( the circuit with the identifed memory elements made scannable ). We can guarantee detection of all irredundant faults as in the Complete Scan Design case, but at significantly less area and performance cost. The length of the test sequences for the faults can be bounded by a prescribed value - in general, a trade-off exists between the number of memory elements required to made scannable and the maximum allowed length of the test sequence.