Logical Design of Digital Systems
Logical Design of Digital Systems
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Automatic Test Pattern Generation with Branch Testing
IEEE Transactions on Computers
Sequential test generation at the register-transfer and logic levels
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Optimal logic synthesis and testability: two faces of the same coin
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Synthesis and optimization procedures for fully and easily testable sequential machines
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
An incomplete scan design approach to test generation for sequential machines
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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The Register level Test Generator (RTG) system is a software tool that automatically develops test patterns to detect all classical single “stuck-at” faults in a digital circuit. In its current state RTG is targeted for boards containing SSI, MSI, and small LSI components. RTG combines an efficient technique for modeling sequential components at the register level with a simple set of testability design rules, and a powerful test generation algorithm. Thus far in its development RTG has been shown to be a useful tool, typically capable of generating a 100% fault coverage test for a 50 IC board in about 30 CPU minutes on a VAX1 11/780 running UNIX.2