RTG: automatic register level test generator
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
EBT: A comprehensive test generation technique for highly sequential circuits
DAC '78 Proceedings of the 15th Design Automation Conference
1985 VLSI Tools: More Works by the Original Artists
1985 VLSI Tools: More Works by the Original Artists
Structured programming
| Hi-index | 14.98 |
The authors present a test algorithm for finite state machines called branch testing. Based on branch testing, a design-for-test (DFT) method is proposed. Comparisons to other DFT methods show the method to be competitive relative to circuit overhead. A minimum set of paths containing all primary and internal gate-level input/output lines is found. Each of these paths is then sensitized so as to detect all single stuck-at faults. The authors demonstrated that the one-hot encoded FSMs can be easily and thoroughly tested via a simple algorithm. It is demonstrated that the use of scan paths is not necessary if a one-hot encoded state assignment is made. The synthesis and simulation resulting have shown that the package of one-hot encoding and branch testing constitutes a viable design and test approach.