MULTES/IS: an effective and reliable test generation system for partial scan and non-scan synchronous circuits

Authors:
T. Ogihara;K. Muroi;G. Yonemori;S. Murai
Affiliations:
ASIC Design Fngineering Center, Mitsubishi Electric Corporation, 5-1-l Ohfuna, Kamkura, Kanagawa, 247 JAPAN;ASIC Design Fngineering Center, Mitsubishi Electric Corporation, 5-1-l Ohfuna, Kamkura, Kanagawa, 247 JAPAN;ASIC Design Fngineering Center, Mitsubishi Electric Corporation, 5-1-l Ohfuna, Kamkura, Kanagawa, 247 JAPAN;ASIC Design Fngineering Center, Mitsubishi Electric Corporation, 5-1-l Ohfuna, Kamkura, Kanagawa, 247 JAPAN
Venue:
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Year:
1989

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Abstract

This paper describes an automatic test generation system which effectively generates test vectors by recognizing the circuit blocks for which vectors are automatically generated and the circuit blocks for which vectors have to be manually prepared.Test vectors for full scan, partial scan and nonscan synchronous circuit blocks are automatically generated. Test vectors for asynchronous circuit blocks have to be manually prepared.