Introduction to an LSI test system
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Automatic checking of logic design structures For compliance with testability ground rules
DAC '77 Proceedings of the 14th Design Automation Conference
Test generation for large logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Tri-state bus conflict checking method for ATPG using BDD
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
PATEGE: an automatic DC parametric test generation system for series gated ECL circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Modeling Custom Digital Circuits for Test
Journal of Electronic Testing: Theory and Applications
Parallel pattern fast fault simulation for three-state circuits and bidirectional I/O
ITC'94 Proceedings of the 1994 international conference on Test
Automatic test pattern generation for asynchronous networks
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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This paper describes a program which generates test patterns for scan design circuits with tri-state modules and bidirectional terminals. The test generation procedure uses a path sensitization technique with 14 signal values. The principal features of this program are test generation with automatic decision of I/O mode of bidirectional terminals, generation of test sets for high impedance state, and generation of test sets for system clock control circuits of shift register latches(SRLs) by using shift-in function of SRLs.