Test generation for scan design circuits with tri-state modules and bidirectional terminals
DAC '83 Proceedings of the 20th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
Design for Testability A Survey
IEEE Transactions on Computers
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For ECL circuits. DC parametric tests such as input current (IIL IIH), reference voltage (VBB), and power supply current (ICC) tests are executed as well as functional tests.This paper describes: an automatic DC parametric test generation system PATEGE for the series gated ECL circuits. PATEGE can automatically generate the test patterns and calculate the expected values for IIL, IIH, VBB and ICC tests.