Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
IEEE Transactions on Computers
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Test pattern generation for sequential MOS circuits by symbolic fault simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Mapping switch-level simulation onto gate-level hardware accelerators
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A switch-level test generation system for synchronous and asynchronous circuits
Journal of Electronic Testing: Theory and Applications
Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates
Proceedings of the IEEE International Test Conference on Test and Design Validity
Algorithms for Switch Level Delay Fault Simulation
Proceedings of the IEEE International Test Conference
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test Pattern Generation with Restrictors
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Extracting gate-level networks from simulation tables
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test generation for scan design circuits with tri-state modules and bidirectional terminals
DAC '83 Proceedings of the 20th Design Automation Conference
Testing "untestable" faults in three-state circuits
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Using Verilog Simulation Libraries for ATPG
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Extraction of Schematic Array Models for Memory Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 1
An integrated system for assigning signal flow directions to CMOS transistors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Redundancy removal and test generation for circuits with non-Boolean primitives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a novel fault simulation environment in VHDL. By writing a library of special fault simulation models, a traditional model is transformed into a new model that performs fault simulation using a VHDL simulation engine. Pre- and post-synthesis ...