Differential fault simulation - a fast method using minimal memory
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Efficient Modeling of Memory Arrays in Symbolic Ternary Simulation
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Using Verilog Simulation Libraries for ATPG
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling Custom Digital Circuits for Test
Journal of Electronic Testing: Theory and Applications
Device and memory array models for flash EEPROM technology
WSEAS Transactions on Circuits and Systems
Device and memory array models for flash EEPROM technology
WSEAS Transactions on Circuits and Systems
| Hi-index | 0.00 |
The modeling and simulation of memory circuits remains an outstanding problem when accuracy with respect to the actual schematic implementation is desired. Functionally equivalent RTL models often cannot be used for designs with embedded memory blocks, because schematic models for the surr ounding logic may be required for fault modeling accuracy. Existing methods derive a latch model that essentially represents each memory location as a latch primitive, and have a large number of gates. We present new algorithms that model such circuits as decoded arrays that access entire rows of cells for individual read and write operations. Decoded array models allow fault modeling accuracy for the surrounding logic, including the memory address decoder. Experimental data show improvements of an order of magnitude for both logic and fault simulations, when compared to the equivalent latch model.